sephiroth said:
the data bus which you describe is not what I'm concerned about. Kentsfield is using a FSB arch that dates back to the Pentium pro.. it consists of two pathways, a quad-pumped data path (that runs @ 266mhz in the case of 1.06ghz FSB cpus, and 333mhz in the case of 1.3ghz FSB cpus) , but the CMD pathway has been left alone.. it still is running at a Single data rate of
266 or 333mhz... If Kentsfield were using HTT vs the P5 FSB arch you'd see an instant 20-80% across the board gain in every application I'd bet.
G80 uses 128 unified shadders

RD600 dosen't really have 64 pixel shadders, since it uses a USA (unified shadder arch) it has dynamic "pipelines" that can adjust to become vertex or pixel shadders, depening on the application. The same goes with the X1900(it uses 48 USA shadders), and G80
Holy hell, good post. Yeah I know goes back to the Pentium Pro 150 way way way back -->P2-->P3-->Tulatin-->then off to the Jews to become the Banias-->then Intel says, ah netburst is to long in the pipeline and too hot let's kill it.-->and the old school becomes new again.
I know about the unified shader stuff to.
Good thing AMD stold some Dec-Alpha guys to help with their first Athlon EV6 bus.
<table class="wikitable"> <tbody><tr><th>Processor Class</th> <th>FSB Frequency</th> <th>FSB Type</th> <th>Theoretical Bandwidth</th> </tr> <tr> <td>
Pentium II</td> <td>66/100 MHz</td> <td>
GTL+</td> <td>533/800 MB/s</td> </tr> <tr> <td>
Pentium III</td> <td>100/133 MHz</td> <td>
GTL+</td> <td>800/1066 MB/s</td> </tr> <tr> <td>
Pentium 4<small>*</small></td> <td>100/133/200 MHz</td> <td>AGTL+</td> <td>3200/4266/6400 MB/s</td> </tr> <tr> <td>
Pentium M<small>*</small></td> <td>100/133 MHz</td> <td>AGTL+</td> <td>3200/4266 MB/s</td> </tr> <tr> <td>
Pentium D<small>*</small></td> <td>133/200 MHz</td> <td>AGTL+</td> <td>4266/6400 MB/s</td> </tr> <tr> <td>
Pentium 4 EE<small>*</small></td> <td>200/266 MHz</td> <td>AGTL+</td> <td>6400/8533 MB/s</td> </tr> <tr> <td>
Intel Core<small>*</small></td> <td>133/166 MHz</td> <td>AGTL+</td> <td>4266/5333 MB/s</td> </tr> <tr> <td>
Intel Core 2<small>*</small></td> <td>166/200/266 MHz</td> <td>AGTL+</td> <td>5333/6400/8533 MB/s</td> </tr> <tr> <td>
Xeon -
P6 core</td> <td>100/133 MHz</td> <td>
GTL+</td> <td>800/1066 MB/s</td> </tr> <tr> <td>
Xeon<small>*</small> -
Netburst core</td> <td>100/133/166/200/266 MHz</td> <td>AGTL+</td> <td>3200/4266/5333/6400/8533 MB/s</td> </tr> <tr> <td>
Xeon<small>*</small> -
Woodcrest core</td> <td>266/333 MHz</td> <td>AGTL+(with Dual Independent Buses)</td> <td>17066/21333 MB/s</td> </tr> <tr> <td>
Athlon/
Duron<small>**</small></td> <td>100/133 MHz</td> <td>EV6</td> <td>1600/2133 MB/s</td> </tr> <tr> <td>
Athlon XP/
Sempron<small>**</small></td> <td>133/166/200 MHz</td> <td>EV6</td> <td>2133/2666/3200 MB/s</td> </tr> <tr> <td>
Athlon 64/
X2/
Opteron<small>***</small></td> <td>600/800/1000 MHz</td> <td>
Hypertransport</td> <td>7500/12800/14400 MB/s</td> </tr> <tr> <td>
PowerPC 970****</td> <td>450/500/625 MHz</td> <td>Elastic</td> <td>7200/8000/10000 MB/s</td> </tr> <tr> <td colspan="4" rowspan="4">
Notes:
<small>* - Pentium 4, Pentium M, Pentium D, Pentium EE, Xeon, Intel Core, and Intel Core 2 processors use a front side bus that transfers data four times per cycle
(omg)</small>NNvidia's upcoming G80 chip should include many things such as 1.35GHz scalable clock for 128 shader units, and a 384-bit memory controller.</td></tr></tbody> </table>